FETs are transistors that use an electrical field to control the electrical behavior of the device. The fin refers in a semiconductor material patterned on a substrate that often has exposed surfaces that form the narrow channel between source and drain region layers. Vertical FETs often include a vertical channel and active source and drain region layers arranged beneath and above the channel. A thin dielectric layer arranged over the fin separates the fin channel from the gate. Like in any transistors, there is a strong need to solve both gate length control and junction position control problems in vertical FETs. In the conventional lateral FinFET transistors, gate length is defined by lithography or sidewall image transfer process. However, in the vertical FET architecture where the channel direction (transport direction) is arranged vertically on the substrate, none of the conventional methods used to define gate length is applicable. The gate spacer thickness and the source-drain extension thickness are also difficult to control in the vertical architecture. It is critical to control them because their thicknesses are closely related to junction positions.